The present invention relates to a device for detecting a difference in bit phase between two identical data sequences each of which is transmitted through a different transmission path.
A device of the kind described is essential in many types of electronic devices which handle data. For example, in a digital microwave communications system having a regular channel and a backup channel, two identical data sequences (hereinafter referred to as data sequences A and B) which are individually transmitted in parallel over the regular and backup channels do not always coincide in bit phase with each other due to a difference in transmission delay between the two independent channels. Moreover, because the difference in transmission delay fluctuates with time, the deviation in bit phase between the data sequences A and B, too, fluctuates with time. Should the regular and backup channels be switched from one to the other while the bit phases are not coincident, a bit error would be caused at the time of switching. To eliminate such bit error, there are performed a sequence of steps: determining whether or not the data sequences A and B are matched in bit phase with each other; if they are not matched, forcibly shifting the relative bit phase until the data sequences become coincident; and thereafter switching from one channel to the other. This function is implemented with a device for detecting bit phase difference.
A prior art device for the detection of a bit phase difference includes a comparator for detecting a bit phase difference between the two data sequences A and B, by determining, whether or not the bit phases of the data sequences A and B are coincident. The prior art device further includes a decision circuit responsive to an output of the the comparator for deciding whether or not the data sequences A and B are matched in bit phase. Such prior art device, however, leaves the following problem unsolved. That is, when the data sequences A and B are each loaded with only a small amount of data, i.e., in a so-called light load condition, the number of data bits per predetermined number of bits of each of the data sequences A and B is decreased. This causes the decision circuit to malfunction and, therefore, to fail to accurately detect a bit phase difference.